1. Field of the Invention
The present invention relates to an application-specific integrated circuit (ASIC) for processing defined sequences of assembler instructions (TASKs).
2. Description of the Prior Art
The performance of a processor is strongly dependent on the memory access times needed to load program code or operands into the processor. Due to slow access times, long dead times arise, particularly in the processing unit (EXU) of a RISC processor which is rapidly clocked. These dead times necessarily lead to a degradation of data throughput.
Different approaches have been suggested to improve the data throughput of a processor. One approach consists in the implementation of expensive cache memory systems. But these cache systems are highly ineffective for applications in which the data is used only once, since a high cache miss rate then arises.
Another approach to increasing the data throughput in I/O processors consists in the execution of a software-controlled TASK change during the execution of a TASK by the EXU, given longer wait times. This TASK change is consequently controlled by the operating system. However, this TASK change regularly requires many additional memory operations for securing and recovering the old and new TASK status, so that this type of TASK change is worthwhile only when given very long wait times, such as in the accessing of external hard disks.
U.S. Pat. No. 4,833,640 discloses a data processing system which comprises a number of register banks in a random access memory (RAM). Access to these register banks and to the registers contained in the register banks occurs according to corresponding processor instructions. The instruction CBNR prompts a change of access from one register bank to another register bank, or a data transfer from a register in one register bank into a register in another register data bank. The register accesses occur under the control of a memory access control circuit and a number of control registers.
German Patent Application No. 43 01 117 discloses a multitasking capable computing device and a method for its operation. The computing device comprises a processor with at least one register set for each TASK to be executed. The computing device also comprises a TASK allocator which assigns the processor that TASK which has the highest precedence rating as the next TASK to be executed.
It is an object of the invention to provide an application-specific integrated circuit (ASIC) having a RISC processor with an improved loading of its internal EXU.
This object is inventively achieved in accordance with the present invention.
Besides a program and data memory, the RISC processor inventively also has an EXU for executing TASKs, in which it is possible to switch to a second TASK during the execution of a first TASK if the execution of the first TASK has been first interrupted. The TASK changeover process is controlled by a TASK scheduler implemented as hardware.
The hardware-controlled TASK changeover offers the advantage that the operating system is relieved from the responsibility of the TASK management, so that it can fulfill other tasks to a greater degree or can be extremely simplified. With the implementation of the TASK scheduler, the entire processing power of the EXU is now available exclusively for handling user firmware.
The TASK scheduler also enables a rather rapid TASK change, i.e. within a few clock cycles, thereby minimizing the dead times of the EXU and maximizing its load or its data throughput.
According to an advantageous development of the TASK scheduler, it comprises a separate TASK controller for each TASK, which detects and controls changes of the current status (RUN, WAIT, READY or HALT) of the TASK allocated to it and which generates a corresponding change information, which is made available to the TASK scheduler. On the basis of this change information, the TASK scheduler controls the changeover process.
Furthermore, an I/O interface is advantageously arranged in the circuit between an external data memory and an internal data bus and has an individual data channel for each TASK. By means of monitoring the data transfer on each individual data channel by the individually allocated TASK controller, a change of the status of the respective TASK can be detected.
It is additionally noted that, for the data transfer between it and the external data memory, the I/O interface advantageously has only one common data channel for all TASKs. By using a common data channel for all TASKs, two interfaces or data channels are saved.
According to an advantageous development of the invention, the circuit comprises register banks which are individually allocated to the TASKs and which are connected to the internal data bus. The register banks store specific data about the status of a respective TASK at the time of its interruption or data which was processed by a TASK prior to its interruption. Due to the use of register banks, a complex memory architecture, which is required in conventional multitasking control systems, is forgone.
According to a particularly simple development of the invention, at least one FIFO memory is provided in the circuit. The FIFO memory is arranged as a unidirectional interface between external components and the internal data bus and which is controlled by a TASK controller which is allocated to it without requiring expensive addressing.